FPP_$CONTROL Domain/OS FPP_$CONTROL
NAME
fpp_$control - modify the floating-point control register
SYNOPSIS (C)
#include <apollo/base.h>
#include <apollo/fpp.h>
void fpp_$control(
fpp_op_t &option,
unsigned long int *control_reg,
status_$t *status)
SYNOPSIS (Pascal)
%include '/sys/ins/base.ins.pas';
%include '/sys/ins/fpp.ins.pas';
procedure fpp_$control(
in option: fpp_op_t;
var control_reg: set_32;
out status: status_$t);
SYNOPSIS (FORTRAN)
%include '/sys/ins/base.ins.ftn'
%include '/sys/ins/fpp.ins.ftn'
integer*4 status, control_reg
integer*2 option
call fpp_$control(option, control_reg, status)
DESCRIPTION
Fpp_$control modifies the floating-point control register to enable or
disable floating-point exceptions. Fpp_$control is for use only with the
DN10000 series and machines equipped with the MC68881 or FPX floating-
point units. When called on other machines, it will return
fpp_$unsupported_operation in status.
option
Specify one of the following predefined values:
read_op
Read the floating-point control register into control_reg.
write_op
Write the floating-point control register from control_reg.
exch_op
Exchange the contents of the floating-point control register
with the contents control_reg.
control_reg
A 32-bit image of the floating-point control register. Only the
least-significant 16 bits are currently used. They are interpreted
as follows:
31 16
______________________________________________________________
| NOT USED |
|_____________________________________________________________|
| (see following tables) |
______________________________________________________________
15 0
_________________________________________________________
| Floating-Point Control Register Exceptions |
| Most-Significant Byte |
|________________________________________________________|
|Bit | Mnemonic and Name | Interpretation |
|____|________________________________|__________________|
| | Branch/Set on Unor- | 0 Disabled |
|15 | BSUN dered Condition | 1 Enabled |
|____|________________________________|__________________|
| | | 0 Disabled |
|14 | SNAN Signaling not a Number | 1 Enabled |
|____|________________________________|__________________|
| | | 0 Disabled |
|13 | OPERR Operand Error | 1 Enabled |
|____|________________________________|__________________|
| | | 0 Disabled |
|12 | OVFL Overflow | 1 Enabled |
|____|________________________________|__________________|
| | | 0 Disabled |
|11 | UNFL Underflow | 1 Enabled |
|____|________________________________|__________________|
| | | 0 Disabled |
|10 | DZ Divide by Zero | 1 Enabled |
|____|________________________________|__________________|
| | | 0 Disabled |
| 9 | INEX2 Inexact Operation | 1 Enabled |
|____|________________________________|__________________|
| | | 0 Disabled |
| 8 | INEX1 Inexact Decimal Input | 1 Enabled |
|____|________________________________|__________________|
_____________________________________________________
| Floating-Point Control Register Exceptions |
| Least-Significant Byte |
|____________________________________________________|
|Bit | Mnemonic and Name | Interpretation |
|____|___________________________|___________________|
| 7 | | 00 Extended |
|____| | 01 Single |
| | PREC Rounding Precision | 10 Double |
| 6 | | 11 Reserved |
|____|___________________________|___________________|
| | | 00 Toward |
| | | nearest |
| 5 | | integer |
| | RND Rounding Mode | 01 Toward zero |
|____| | 10 Toward minus |
| | | infinity |
| 4 | | 11 Toward plus |
| | | infinity |
|____|___________________________|___________________|
| 3 | | |
|____| | |
| 2 | | |
|____| | NOT USED |
| 1 | | |
|____| | |
| 0 | | |
|____|___________________________|___________________|
status
The completion status.