NAME

cpmex1.diag, cpmex2.diag − Test CPU response to exception conditions

DESCRIPTION

Tests the error detecting and error generating logic on the CPU board, the error detecting and error generating logic on the first memory board, and the bus interface logic on the CPU and the memory board that has the lowest logical memory ID number. 

The tests cpmex1.diag and cpmex2.diag are separate parts of a single test suite.  Both CPU and Memory exception tests are performed.  These tests are designed to deliberately force error conditions to occur (1) when the CPU is sending data to the memory to test that the memory detects the errors, and (2) to force errors to occur when the Memory sends data back to the CPU so that the CPU detects the error. 

DETAILS

Because the tests cause errors that convince the CPU that the data coming across the bus is bad, the actual program code cannot be loaded into the normal system memory space.  Therefore the tests are loaded into the instruction cache on the CPU board.  This allows the program code to be run without accessing the system memory bus.  Because of the limited memory space available in the cache, the tests were split into two parts.  Thus the names cpumex1.diag and cpmex2.diag, each of which runs a separate part of the exception tests. 

When errors occur, they appear in four possible places:

•The S Bus Status Register on the CPU board

•The S Bus Status Register on the Memory board

•The Integer processor’s Status register

•The Integer processor’s Cause register

The general test method is as follows:

•Use the CPU board Test Register to force data transfer errors on data sent from the CPU. 

•Use the Memory board PECTL register to force data transfer errors on data sent from the Memory to the CPU. 

•Check the values in each of the error status registers specified above for expected values versus the actual value that is received, masking off the bits that have no bearing on the test.  These unused bits are called don’t care bits. 

BOARDS THAT MUST BE INSTALLED

One CPU board, one memory board, and a known good I/O board for downloading the test.  If more than one memory board is installed, these diagnostics test only that memory board that has the lowest ID number. 

SPECIAL COMMAND LINE PARAMETERS

Do not specify all on the command line.  If the all menu item is chosen from the menu and a test fails, the tests must be run individually to determine which of the tests in that menu is actually failing.  There is no progress message generated indicating which of the menu−selectable tests is being conducted. 

MENU ITEMS SPECIFIC TO THIS TEST

Test menu for cpmex1.diag. 

sr −This test reads the Scrub Register. The test performs a read of a write−only register to test the exception condition illegal operation. 

sa −This test forces an alignment error during a memory scrub operation. 

wa −This test forces an alignment error during a write to memory. 

rdp −This test forces a data parity error on a read from memory. 

rap −This test forces an address parity error on a read from memory. 

wdp −This test forces a data parity error on a write to memory. 

wap −This test forces an address parity error on a write to memory. 

ra −This test forces an alignment error on a read from memory. 

wl −This test forces an alignment error on a write to memory. 

Test menu for cpmex2.diag. 

la −This test forces an alignment error on a load and sync operation. 

le −This test forces an ECC error during a load and sync operation. 

se −This test forces an ECC error during a Scrub ECC operation. 

cr −This test creates a reserved Cycle Type exception on a read. 

cw −This test creates a reserved Cycle Type exception on a write. 

re −

bt −This test creates a bus timeout. 

INTERPRETING THE ERROR CODES

The following errors may be generated by this test.  (The actual error wording may differ, however the type of error is as summarized here.) 

100Memory error, reports physical address for the error, the actual data and the data that was expected. 

121The test that is being performed failed to get an expected interrupt.  This is the error code that is reported when the Integer Processor cause register does not get the expected value. 

122CPU Board S Bus Status register did not contain the expected value.  This error report contains the actual value, the expected value, and the don’t care bits so that the bit-in-error can be determined. 

142IPU Cause register did not contain the expected value.  Reports actual, expected and don’t care bits for the register. 

152Memory S Bus Status register did not contain the expected value.  Reports actual, expected and don’t care bits for the register. 

162Memory is operating at 16-way interleave.  This test cannot be run when 16-way interleave is active.  Power down the machine and remove all except one of the memory boards, power up and try again. 

EXAMPLES

This section contains the actual bit patterns for the S Bus Status registers and the CPU Cause register, along with an explicit sample that shows how the bits are interpreted. 

Processor Status Register (contains CPU S Bus Status)
Bit
 31  30  29  28  27  26  25  24 23-16 15-8       7-0
NXA BTO DPE APE ITT AAE RPE BRD  zero ProcStatus ProcControl

Memory Board Status Register (contains Memory S Bus Status)
Bit
 31  30  29  28  27  26  25  24 23-16 15-8       7-0
  0   0 DPE APE ITT AAE RPE BRD ReqID IntlvErr   BoardControl

Cause Register (inside the Integer Processor Chip)
Bit
31-6         5-2            1-0
Not tested   ExceptionCode  Not Tested

September 02, 1992