NAME

cpu.diag − Test the circuitry on the CPU board

DESCRIPTION

This test checks various registers and interrupt sources.  It does not, however, test the CPU’s response to exception conditions.  A pair of tests, cpmex1.diag and cpmex2.diag handle this exception testing.  The following items are tested here:

• Boot PROM

• LED Register

• CPUID PROM

• ID Register

• S Bus Status Register

• Doorbell Register

• Semaphore Address Register

• External Translation Lookaside Buffer (ETLB)

• Processor ID Register

DETAILS

The following lists the kinds of tests that are performed for each of the above entities on the CPU board. 

• Boot PROM
A checksum is performed.

• LED Register
The individual bits are tested to assure that all LEDs can be lit or extinguished.

• CPUID PROM
The types of entries in the PROM are checked and the ethernet address in the PROM is output.

• ID Register
This test reports the ID value of the CPU that is running the test and the slot number in which it is installed.

• S Bus Status Register
By either directly writing bits into the S Bus Status register or by using the Test Register to set various bits, various error types that are supposed to be sensed by the S Bus Status Register are tested.  This test also checks that the appropriate interrupt is generated when various error types are simulated.

• Doorbell Register
This test checks the ability of the CPU to respond correctly to ringing of the CPU’s doorbell.  Ringing the doorbell causes an interrupt to occur and directs the CPU to begin execution of a function at a specific address in response to the interrupt. If there is more than one CPU installed (and active) in the system, the other CPU’s doorbells are rung also, checking that they respond as expected.  Note that this is the only test, within the cpu.diag sequence, during which multiple processors are tested.  If you wish to run cpu.diag on each processor in a multi-processor system, you will have to run the test with each processor individually as the boot processor.  This requires either turning off the power and physically moving the CPU board to the boot processor slot (whichever slot has the lowest slot ID, usually slot 4 is used), or disabling the current boot CPU card and rebooting the system.

• Semaphore Address Register
Testing this register assures that the CPU will be able to use it to access memory locations that are specified for semaphore operation.

• External Translation Lookaside Buffer (ETLB)
The tests on the ETLB include testing of the ETLB memory and all registers associated with address translation for the vector processing unit.

• Processor ID Register
This test checks that the process ID register can contain all possible values that can be assigned to process ID.

BOARDS THAT MUST BE INSTALLED

Requires one CPU board, one memory board, and a known good I/O Board for downloading the test. 

SPECIAL COMMAND LINE PARAMETERS

None

MENU ITEMS SPECIFIC TO THIS TEST

idpTests the CPU ID PROM

idrTests the CPU ID Register

bsrTests the S Bus Register

sbiTests the S Bus Interrupts

dbRuns the doorbell test

semPerform the semaphore register test

etPerform the ETLB tests

ledPerform the LED test

pidTest the PID register

chkChecksum the boot PROM

INTERPRETING THE ERROR CODES

The following errors may be generated by this test.  (The actual error wording may differ, however the type of error is as summarized here.) 

100SBStatus bit test FAILED

102??? 

104Semaphore Address test failed.  Reports the bits in error. 

106,108
CPUID Register test failed.  Reports the bits in error.

110Card type is supposed to be "CPU", (card type value = 1), but a different card type was found in the CPU ID Register. 

112,114,116,118
??? ERROR 112 - ACT: %08x, EXP = %08x, Not Tested: %08x0, HE, value,ETLBCONT_MBZ,ETLBCONT_DT);
ERROR 114 - ACT = %08x, EXP = %08x, Not Tested: %08x0, HE, value,ETLBCONT_MBZ,ETLBCONT_DT);
ERROR 116 - ACT = %08x, EXP = %08x, Not Tested: %08x0,
ERROR 118 - ACT = %08x, EXP = %08x, Not Tested: %08x0,

120-126
The ETLB has been tested for accuracy of its address translation capability.  Any failures report the failing address, along with the actual and expected values.

128-134
The ETLB has been tested as memory, through the ExtEntryHi register. Any failures report the failing address, along with the actual and expected values.

138-142
The ETLB has been tested as memory, through the ExtEntryLo register. Any failures report the failing address, along with the actual and expected values.

144An exception did not occur when an attempt was made to write to a read-only page. 

146,150,154
Incorrect value found in testing the ETLB Condition register.

148,152
Incorrect value found in testing the CPU Status register.

156During a test of the ETLB condition register, the test should have generated a non existent address status, but the NXA bit did not get set. 

158The entries in the ETLB were declared as invalid, but when access to an invalid address was attempted, an exception (invalid entry) did not occur. 

160,162
During invalid entry testing of the ETLB, the ETLB condition register or the CPU Status register had an incorrect value. The incorrect bits are reported.

164Incorrect value found while testing the S Bus ETLB condition register. 

166Expected an NXA during testing that invalid PID causes an interrupt and that global matches allow any PID match to succeed.  NXA did not occur when expected. 

168Exception should have occured when generating a Semaphore PID miss. 

170Incorrect value (no exception occured) when attempting to match an invalid PID in non-global mode. 

172CPU status register contains an incorrect value when attempting to match an invalid PID in non-global mode. 

174,176,178
Exception not caused when trying to match an invalid PID in non-global mode.

180Incorrect response to ringing one’s own doorbell register. 

182Incorrect response to ringing another processor’s doorbell.  The failing processor number is reported. 

184-196
An unexpected type of exception occurred.  The contents of the various exception and status registers are printed for examination.  The registers dumped are the frame, cause_code, status, cause, and the CPU status register.

200Incorrect PROM Checksum was found.  Actual and expected value are reported. 

210No ID PROM was found. 

212Bad checksum in the CPU ID PROM. 

215-275
These error codes report lack of expected exceptions that should have occured as a result of S Bus Status register (in conjunction with Test Register) error forcing.

300,305,310
Expected exception did not occur while performing Semaphore access.

September 02, 1992