NAME

iobuscv.diag − Tests the bus converter on the I/O board

DESCRIPTION

There are several sources for DMA data transfer to an internal ("micro bus") bus on the I/O board.  This test checks that each possible source of DMA is functional, that the bus arbitration on this internal bus is functional, and that the conversion from Titan Bus to the internal bus (and vice versa) works correctly. 

DETAILS

None

BOARDS THAT MUST BE INSTALLED

This test requires a CPU board, a memory board and the I/O board. 

SPECIAL COMMAND LINE PARAMETERS

None

MENU ITEMS SPECIFIC TO THIS TEST

adAddress path test.  Check that writing addresses to the DMA controller results in the correct addressed location being accessed. 

daData path test.  Check that the data registers in the DMA controller are functional. 

dmDma test.  Data is written from I/O to memory and the memory copy of the data is checked for accuracy. 

ovOverlapped buffer test.  Two channels are set up to do overlapped DMA and the correct operation is verified. 

caDMA cache test. 

INTERPRETING THE ERROR CODES

The following errors may be generated by this test.  (The actual error wording may differ, however the type of error is as summarized here.) 

101While testing a specified register location, an unexpected value was found. 

103The program wrote to register dc_marhi (address 10fffd00c), and the value read from that same location yielded different data than was written. 

105The program wrote to a register at location 10fffd00d, and it unexpectedly changed the value stored at 10fffd00c. 

107The data written to 10fffd00d was read back and found to be different than expected. 

109A walking-ones test was performed on the data registers.  The data read back did not match the data written.  The actual and expected values are reported. 

123The DMA controller is reset, and the system expects to find the DMA interrupt cleared.  However, an interrupt bit (DMA03) was found to be set anyway. 

125During an overlapped DMA test, the data read back was not the same as that written.  The differences are reported. 

127After an appropriate waiting time, it was found that a DMA operation did not complete. 

129The DMA finished, but an error was reported.  The error is specified with this error message. 

131This is a continuation of error 129 in that the contents of all of the DMA registers is reported. 

133A DMA was performed and the data read back was not the same as the data that was written.  The location of the bad data, along with the actual and expected values, is reported. 

139The DMA controller was reset, but not all of the interrupt bits were cleared. 

141Following the dma cache test, the register contents was not as expected.  The actual and expected values are reported. 

September 02, 1992