NAME

lance.diag − Ethernet interface test

DESCRIPTION

This diagnostic tests the Ethernet and Cheapernet interface.  For one of the tests, either a transceiver cable with a tap for the Ethernet interface or a terminator for the Cheapernet interface must be provided (external loopback test).  Note that the address mapper test (mapper.diag) should be performed first to verify correct operation of the I/O Mapper since this circuitry is used during the test. 

DETAILS

This Ethernet/LANCE Testing/Bring-up Program can be called as either a cache test or a PROM test/diagnostic.   The tests proceed as follows:

1)Read/Write LANCE registers and verify

2)Try to load the init block through each entry in the I/O mapping table.  For a memory-less test, we expect these to always fail.  For memory, these must always succeed. 

NOTE:   A memory-less test (run from cache) will go no farther. 

3)Internal Loopback
•   Check the CRC generated by the chip when
transmitting

4)External Loopback is tested two different ways,
•   Check the CRC generated by the chip when
transmitting
•   Check the CRC checking when receiving

5)If all the above tests have succeeded, the system will attempt to PING to a user-specified site until the user interrupts. 

BOARDS THAT MUST BE INSTALLED

This diagnostic needs the CPU board, at least one memory board, and the I/O board. 

SPECIAL COMMAND LINE PARAMETERS

allIf you specify all on the command line, the lance.diag executes all tests on the menu except the signal test.  If this test is loaded from the DCP, the argument all is ignored. 

MENU ITEMS SPECIFIC TO THIS TEST

lrRead/write lance registers" Performs Read/Write pattern tests on the on the Lance register. 

inThis test initializes the lance through the I/O address mapper.  It loads the initialization block through each entry in the address mapper.  The purpose of the test is to check the DMA path, and to examine basic function of the Lance chip. 

ilThis test is called the internal loop back test.  The LANCE chip is programmed for the internal loop back mode that allows the chip to receive its own transmitted packet.  Some test patterns are transmitted and received within the chip and verified.  This test dose not need an external transceiver cable or a tap. 

elThis test is called the external loopback test" The LANCE chip is programmed for the external loop back mode that allows the chip to transmit a packet through a transceiver cable out to the Ethernet coaxial cable and then to received its packet through the transceiver cable.  This test examines the operationability of all Ethernet interface and connections through the coaxial cable.  Also, CRC generation logic and CRC check logic are tested individually.  The external test may fail with a heavy traffic cable, and cause warning message such as "#WARNING retrying ...".  According to the data sheet of the LANCE chip, it is not an error, but it must not happen with an isolated cable.  In the current implementation, the program allows consecutive 10 retries with warning messages, and judges 11th retries as an error. 

allAll executes all tests on the menu except the signal test. 

INTERPRETING THE ERROR CODES

The following errors may be generated by this test.  (The actual error wording may differ, however the type of error is as summarized here.) 

101During the lance register test, the program was unable to clear an interrupt that was pending to the lance present when the test was started.  Prior to this error report, the user will be told that an unexpected lance interrupt was pending and that this test would clear that interrupt before attempting to proceed. 

103During lance register testing, reading back the CSR0 register yielded a value different than that written. 

105During lance register testing, reading back the CSR3 register yielded a value different than that written. 

107During lance register testing, reading back the CSR1 register yielded a value different than that written. 

109During lance register testing, reading back the CSR2 register yielded a value different than that written. 

111Note: Error codes 111−129 are for the internal loopback test.  During attempt to initialize lance through the I/O mapper, the correct operating mode bits did not become set.  Attempted to set both MODE_DRX and MODE_DTX, but no other mode bits.  Internal loopback mode initialization. 

112An interrupt was expected during the lance initialization routine, but it did not happen. 

113,114
An incorrect return value was received from the lance following initialization.  The addressed location and the expected value are reported.

115Attempted to force a lance interrupt and it did not occur. 

117Attempted to force a lance interrupt and got a different interrupt instead. 

119Attempted to force a particular lance interrupt and got a different lance interrupt.  The failing pattern and lance status are reported. 

121Expecting a lance transmit buffer empty interrupt but it was not received.  The lance status is reported. 

123Checking the lance transmit descriptor during loopback testing to see if the message header says that the message belongs to lance.  Message descriptor value is incorrect. 

125The destination address in the message header was not correct.  Prints the actual and expected value. 

127The lance had a data error, the data pattern received was not the same as the pattern that was sent. 

129The CRC value (error checking code) of the message was incorrect. 

131Lance initialization failed during setup for external loopback test. 

133Expected lance interrupt did not happen. 

135Attempted to force a lance interrupt and got a different interrupt instead. 

137Attempted to force a particular lance interrupt and got a different lance interrupt.  The failing pattern and lance status are reported. 

139,143
Performing the external loopback test with a loaded cable.  The number of retries has exceeded the count of 10 so it is assumed that either the cable is extremely busy or there is some other error, possibly with the cable or transceiver.  Retries occured following a BABL or MISS, or with a retryable transmit error.  Status values in various lance registers are reported along with this error.

141Same as 121 except is for the external loopback test. 

145Same as 125 except is for the external loopback test. 

147Same as 127 except is for the external loopback test. 

149Same as 129 except is for the external loopback test. 
 
 

September 02, 1992