NAME

svagsb.diag − Test the D store pipe on the Boot CPU. 

DESCRIPTION

This test generates random patterns in the vector registers, and directs the “D” load pipe to store to various memory areas, checking that the results of the store are as expected.  In other words, did the vector address generators actually direct the contents of the vector registers to the correct locations in memory. 

DETAILS

none required. 

BOARDS THAT MUST BE INSTALLED

This test requires a CPU card, and at least one memory card to be present in the system.  If more than one CPU card is to be tested, the individual cards must be tested separately by making each, in turn, the boot processor. 

SPECIAL COMMAND LINE PARAMETERS

None

MENU ITEMS SPECIFIC TO THIS TEST

lv1One set of tests of loading random sets of vector registers from random memory locations. 

lv2−lv6
Identical to lv1 except that the random number generator is started with a different random seed value. 

INTERPRETING THE ERROR CODES

The only error type reported here is that the actual value did not equal the expected value.  The error reporting includes the source line in the verilog test script the actual value read and the expected value.  The script must be examined to determine what type of testing is being performed. (Test script not provided to customers — a failure only indicates that the CPU board has a problem and should be replaced).  This error could indicate an error either in the load pipe circuitry, the memory, the ETLB circuitry, the vector register memory or anywhere in between. 

September 02, 1992