FPGALOAD(8)
NAME
fpgaload − configure FPGA
SYNOPSIS
auxi/fpgaload [ -c clk ] file.rbf
DESCRIPTION
Fpgaload configures the directly-attached Altera Flex6000 FPGA on the Bright Star Engineering ip-Engine. It enables the FPGA and output of the external system clocks, then loads the FPGA with the contents of file.rbf which should be in the ‘raw binary format’ produced for example by the Altera tools. After successful configuration, the BCLK is set to clk MHz; clk must be a divisor of the ip-Engine’s system clock (currently 48 MHz).
SOURCE
/appl/cmd/auxi/fpgaload.b